1. Field of the Invention
This invention relates to a substrate of semiconductor package for Flip Chip package, and more particularly to a substrate of semiconductor package for Flip Chip package having bump pad with etching hole.
2. Description of Related Art
In the information explosion of the world nowadays, the integrated circuit has become indispensable in our daily life, regardless of our daily life in food, clothing, lodging, transportation, education, and entertainment, the product assembled by various integrated circuit devices can be found. everywhere. Following the evolution of the electronic technology, more sophisticate electronic products with user friendly and complicated functions are continuously progressing and changing. Nevertheless, in order to provide an ongoing convenience and comfortable usage, all the products are heading for the design trend of xe2x80x9cLight, Thin, Short, and Smallxe2x80x9d. In addition, the fabrication process of semiconductor has stepped into the mass production era of 0.18 xcexcm integrated circuit, and semiconductor products with even higher integration have become at hands easily. As for packaging technology of the back end semiconductor process, there are many successful cases on the development of precise package structure, i.e. chip scale package (CSP), wafer level package, and Multi-Chip Module (MCM) etc. However, in respect of the assembly technology of devices, there is also a multi-level printed circuit board (PCB) with even higher density which make the integrated circuit (IC) package even closely and densely dispose on the printed circuit board.
Nevertheless, a Flip Chip technology is the one that is frequently used on the package technology of CSP. As the Flip Chip Technology can employ area array to dispose bump pad and be connected to the carrier through a bump, it can reduce the packaging area and shorten the transmission path of the signal. The effect of the current product on the bump""s collapse will depend on the extent that the solder mask covers the bump pad. Traditional type of bump pad design of the substrate can be classified into SMD (Solder Mask Define) type and NSMD (Non Solder Mask Define) type. Each of these two types of bump pad design has its own merits and demerits, thereby, there is no verdict on this matter one way or another.
FIG. 1A and FIG. 1B are both a cross-sectional view of a Flip Chip package taking NSMD as an example according to the prior art. As shown in FIG. 1, a plurality of bumps 102 is formed on the active surface 101 of a chip 100. The conventional Flip Chip package structure frequently employs laminate substrate 108 having relatively high integration to be a carrier. Generally, a substrate 110 is composed of a copper foil pattern layer having a plurality of patterns, and an insulative layer alternately stacking up each other, together with etching holes (not shown) for connecting the pattern layers. The substrate 110 has its surface coated With a solder mask layer, and exposes only the bump pads. In this way, the chip 100 is having its active surface 101 attached to the substrate 110 and is electrically connected to bump pads 106 by its bumps 102.
In addition, an underfill material (not shown) is employed to fill the space between the chip 100 and the substrate 110. This is to protect the bumps 102 from being xe2x80x9cfatigue collapsexe2x80x9d due to the thermal stress resulted from the difference between the coefficient of thermal expansion of the chip 100 and that of substrate 110. Besides, in the Flip Chip package products, since Pb-Sn (Lead-Tin) bumps are in ball shape, and as the chip having bumps formed thereon is attached to the substrate, position offset of either left-offset or right-offset may occur between the bump and the bump pad. Besides, elevation offset generated by the coplanarity due to the substrate itself or between the adjacent bumps may also occur.
As shown in FIG. 1B, a conventional method is to employ a Reflow Process to heat the bump 102 such as Pb-Tin bump to be higher than 183xc2x0 C. to be melted, and to be heated to be higher than 200xc2x0 C. to have a good Wetting function. If any elevation offset occurs resulted from the coplanar problems when the chip is placed on the bump pad such that part of the bumps 102 are unable to touch the bump pads 106, or the bumps 102 are able to touch the bump pads 106 but the contact areas are too small to have a good contact between the bumps 102 and the bump pads 106, in this case, although the reflow process is employed to have a lot more time to heat the bumps 102 to be higher than 200xc2x0 C., the problems of being bad contact or too large in electrical contact resistance between the bumps 102 and bump pads 106 can not yet to be effectively improved. Consequently, the bumps 102 are cracked due to the thermal stress caused by the bad solder joint between the bumps 102 and the bump pads 106, thereby, the electrical conductance is affected and the corresponding yield is low.
Therefore, it is the one of the objectives of the present invention to provide a substrate of semiconductor package for Flip Chip package to improve the solder joint liability between the bumps and the bump pads, and to raise the yield.
In order to attain the foregoing and other objectives, the present invention provides semiconductor package structure for Flip Chip package that includes at least an insulative core layer and a plurality of patterned circuit layers alternately stacking up each other. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of bump pads and each of the bump pads has an etching hole. The solder mask layer covers the surface of the patterned circuit layer and a portion of the surface of the outer edge of the bump pads, and exposes the etching holes. The solder mask layer may also expose the whole surface of the bump pads.
According to a preferred embodiment of the present invention, since the substrate of the semiconductor package for Flip Chip package has etching holes, when the bumps attach the bump pads, the bumps will penetrate into the etching holes. Therefore, the contact area between the bumps and the bump pads is not limited to the top surface of the bump pads, but the contact area also includes the interior surfaces of the etching holes. The contact area between the bumps and the bump pads even includes the side surfaces of the bump pads for NSMD type of package substrate. Since the contact area between the bumps and the bump pads increases, the solder joint reliability can be improved and the yield and the reliability of the package can also be improved.